A programmable logic device (PLD), such as a Field Programmable Gate Array (FPGA), is an integrated circuit (IC) that is programmed to perform specified logic functions. The PLD typically includes an array of programmable logic blocks that are programmed with an intellectual property (IP) core. It is appreciated that the IP core is typically proprietary configuration data used for performing a variety of commonly-used functions. The IP core can be vendor-provided and sold either by a manufacturer of the PLD or by a third party, freeing a customer of the manufacturer from needing to program the functions on their own.
Generally, an IP core includes a predetermined set of configuration data bits that program the PLD to perform one or more functions. Logic and connectivity of a design in the PLD can be represented by or be mapped by the IP core. The IP core can provide Digital Signal Processing (DSP) functions, storage function, logic functions, and math functions.
The PLD is typically configured using a dedicated controller (sometimes referred to as a “control block” or “control circuit”). In conventional controller architecture, the IP cores are typically built together in a single block along with other configuration logic. Due to the requirement of the IP cores and the other configuration logic to support various device features, the controller can take up a significant amount of device area in an IC device.
When the IC device is initialized during power up, there are times when some or all of these IP cores are not used or required by the controller. In this case, the unused IP cores still permanently exist in the controller even when the IP cores are disabled from operation. Such a configuration leads to an unnecessary increase of the device area, which subsequently results in an increase in device fabrication cost.